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DIN EN 61523-2:2003-06
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries (IEC 61523-2:2002); German version EN 61523-2:2002, text in English
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Summary
This standard specifies the pre-layout delay calculation method for CMOS1 ASIC Libraries which contains cell based primitives and memories to be used during the pre-layout design phase of Logic simulation, Timing verification, and Logic synthesis.
Technical characteristics
| Publisher | Deutsche Institut für Normung e.V. (DIN) |
| Publication Date | 06/01/2003 |
| Page Count | 40 |
| EAN | --- |
| ISBN | --- |
| Weight (in grams) | --- |
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