Superseded
Draft standard
Historical
DIN IEC 62659:2013-09
Nanomanufacturing - Large scale manufacturing for nanoelectronics (IEC 113/171/CD:2012)
Summary
This standard provides a framework for introducing nanoelectronics into large scale, high volume production in semiconductor manufacturing facilities through the incorporation of nanomaterials (e. g. CNT, graphene, quantum dots, etc.) (fabs). Since semiconductor fabs must incorporate practices that maintain high yields, there are very strict requirements for how manufacturing is performed. Nanomaterials represent a potential contaminant in semiconductor fabs, and must be introduced in a structured and methodical way. This standard suggests generic steps that might be employed to facilitate the introduction of nanomaterials into the fabs. This sequence is described below under the areas of Raw Materials Acquisition, Materials Processing, Design, IC Fabrication, Testing, and End-Use. These activities represent the major stages of the supply chain in a fab.
Technical characteristics
| Publisher | Deutsche Institut für Normung e.V. (DIN) |
| Publication Date | 09/01/2013 |
| Page Count | 21 |
| EAN | --- |
| ISBN | --- |
| Weight (in grams) | --- |
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Previous versions
01/09/2013
Superseded
Historical