IEC 63011-1:2018
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IEC 63011-1:2018

IEC 63011-1:2018 Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology

Summary

IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.

Technical characteristics

Publisher International Electrotechnical Commission (IEC)
Publication Date 11/28/2018
Edition 1.0
Page Count 24
EAN ---
ISBN ---
Weight (in grams) ---
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